Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. The interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. The interconnects formed in different layers can be electrically connected using vias or contacts. A conductive material filling process of such features, i.e., via openings, trenches, pads or contacts can be carried out by depositing a conductive material over the substrate including such features.
Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The preferred method of copper deposition is electrodeposition. During fabrication, copper is deposited on the substrate that has been previously coated with a barrier layer and then a seed layer. Typical barrier materials generally include tungsten, tantalum, titanium, their alloys, and their nitrides. The deposition process can be carried out using a variety of processes. After depositing copper into the features on the semiconductor wafer surface, an etching, an electro polishing or a chemical mechanical polishing (CMP) step may be employed. These processes remove the conductive materials off the field regions of the surface, thereby leaving the conductive materials only within the via, trench and other features. During such removal processes, the use of electrodeposition processes that yield planar and defect free copper layers prevents material losses improves throughput while reducing cost.
The importance of overcoming the various deficiencies of the conventional electrodeposition techniques is evidenced by technological developments directed to the deposition of planar copper layers. U.S. Pat. No. 6,176,992 to Talieh, entitled “Method and Apparatus for Electrochemical Mechanical Deposition” and commonly owned by the assignee of the present invention, describes in one aspect an electro chemical mechanical deposition technique (ECMD) that achieves deposition of the conductive material into the cavities on the substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited, thus yielding planar copper deposits.
U.S. application Ser. No. 09/740,701 now U.S. Pat. No. 6,534,116 entitled “Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence,” also assigned to the same assignee as the present invention, describes in one aspect a method and apparatus for plating a conductive material onto the substrate by creating an external influence, such as causing relative movement between a workpiece and a mask, to cause a differential in additives to exist for a period of time between a top surface and a cavity surface of a workpiece. While the differential is maintained, power is applied between an anode and the substrate to cause greater relative plating of the cavity surface than the top surface.
U.S. application Ser. No. 09/735,546 now U.S. Pat. No. 6,482,307 entitled “Method and Apparatus For Making Electrical Contact To Wafer Surface for Full-Face Electroplating or Electropolishing” filed on Dec. 14, 2000 describes in one aspect a technique for providing full face electroplating or electropolishing. And U.S. application Ser. No. 09/760,757 now U.S. Pat. No. 6,610,190 entitled “Method and Apparatus for Electrodeposition of Uniform Film with Minimal Edge Exclusion on Substrate” filed on Jan. 17, 2001 describes in one aspect a technique for forming a flat conductive layer on a semiconductor wafer surface without losing space on the surface for electrical contacts.
Further, U.S. patent application Ser. No. 09/511,278 now U.S. Pat. No. 6,413,388 entitled “Pad Designs and Structures for a Versatile Materials Processing Apparatus” filed Feb. 23, 2000, and U.S. patent application Ser. No. 09/621,969 now U.S. Pat. No. 6,413,403 entitled “Pad Designs and Structures With improved Fluid Distribution” filed Jul. 21, 2000, and both assigned to the same assignee as the present invention, describe, among other aspects, pad designs that assist in providing surface with a uniform material overburden. In particular, FIG. 12 of U.S. patent application Ser. No. 09/511,278 shows channels in the form of slits 120 and circular openings 121.
While these techniques assist in obtaining planar metal deposits on wafers, there is still a need for further development of high-throughput techniques and devices that can yield planar metal deposits with better uniformity.